Verilog-to-Routing

Verilog to Routing
Developer(s) The VTR Development Team
Stable release
7.0.7 / October 2013 (2013-10)
Development status Active
Written in C/C++
Operating system Unix-like
Type Electronic Design Automation
License MIT License
Website verilogtorouting.org

Verilog-to-Routing (VTR) is an open source CAD flow for FPGA devices.[1][2] VTR's main purpose is to map a given circuit described in Verilog, a Hardware Description Language, on a given FPGA architecture for research and development purposes. The VTR project is a collaboration between the University of New Brunswick, the University of California, Berkeley and the University of Toronto. Additional contributors include Altera and Texas Instruments.

VTR Flow

The VTR design flow consists of three component applications: ODIN II which compiles Verilog code to a circuit in Berkeley Logic Interchange Format (BLIF), a human-readable graph representation of the circuit;[3] ABC which optimizes the BLIF circuit produced by ODIN II; and VPR which packs, places and routes the optimized circuit on the given FPGA architecture.

ODIN II

ODIN II is the HDL compiler of the VTR flow. It transforms a given Verilog code to a BLIF circuit, performs code and circuit optimizations, visualizes circuits,[4] and performs partial mapping of logic to available hard blocks of the given architecture. Also, it can simulate the execution of circuits both for validation as well as power, performance and heat analysis. ODIN II is maintained by the University of New Brunswick.[5]

ABC

ABC optimizes BLIF circuits by performing logic optimization and technology mapping. ABC is maintained by the University of California, Berkeley.[6]

VPR

Versatile Place and Route (VPR) is the final component of VTR. Its input is a BLIF circuit, which it packs, places and routes on an input FPGA architecture.

During packing, neighboring and related logic elements of the circuit are clustered together into Logic Blocks matching the hardware of the FPGA. During placement, these logic blocks as well as hard blocks are assigned to the available hardware resources of the FPGA. Finally, during routing the signal connections between blocks are made. VPR is developed by the University of Toronto.[7]

See also

References

  1. ↑ "VTR 7.0: Next Generation Architecture and CAD System for FPGAs". ACM Trans. Reconfigurable Technol. Syst. 7: 6:1–6:30. 2014.
  2. ↑ "The VTR project: architecture and CAD for FPGAs from verilog to routing". Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays. 2012.
  3. ↑ "Berkeley logic interchange format (BLIF)". Oct Tools Distribution. 2: 197–247. 1992.
  4. ↑ "Visualization support for FPGA architecture exploration". 23rd IEEE International Symposium on Rapid System Prototyping (RSP): 128–134. 2012.
  5. ↑ "Odin II-an open-source verilog HDL synthesis tool for CAD research". 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM): 149–156. 2010.
  6. ↑ "A system for sequential synthesis and verification". Berkeley A. B. C. 2009.
  7. ↑ "VPR: A new packing, placement and routing tool for FPGA research". Field-Programmable Logic and Applications. Springer Berlin Heidelberg. 1997.

External links

This article is issued from Wikipedia - version of the 10/31/2016. The text is available under the Creative Commons Attribution/Share Alike but additional terms may apply for the media files.