Saraju Mohanty

Saraju Mohanty

Prof. Saraju P. Mohanty in 2012
Born Odisha, India
Residence Denton, Texas, United States
Nationality United States United States
Alma mater University of South Florida (USF), Tampa
Indian Institute of Science (IISc), Bangalore
Orissa University of Agriculture and Technology (OUAT), Bhubaneswar
Occupation Professor, Author, Scientist, Engineer, Computer engineer
Faculty University of North Texas
Known for Mixed-Signal Systems, Nanoelectronics Systems, Metamodeling, Design for X, High-level synthesis (HLS), Hardware-assisted Digital watermarking
Notable work Nanoelectronic Mixed-Signal System Design, McGraw-Hill, 2015, ISBN 978-0071825719
Spouse(s) Dr. Uma Choppali
Honors

The 2016 PROSE Award for best Textbook in Physical Sciences & Mathematics from the AAP.
The 2016-17 Toulouse Scholars Award from UNT.
Editor in Chief (EiC) of the IEEE Consumer Electronics Magazine (MCE).
Chair of the Technical Committee on VLSI (TCVLSI), IEEE Computer Society (IEEE-CS).

President's Scout Award in 1988 from then President of India, President R. Venkataraman.
Website www.smohanty.org

Saraju Mohanty is an American Professor of the Department of Computer Science and Engineering (CSE), and the Director of the NanoSystem Design Laboratory (NSDL), at the University of North Texas (UNT) in Denton, Texas.[1][2] Professor Mohanty is a researcher in the areas of "Low-Power High-Performance Nanoelectronics Systems" and "hardware-assisted Digital watermarking".[3] He has made significant research contributions to Analogue electronics and Mixed-signal integrated circuit Computer-aided design (CAD) and Electronic design automation (EDA), nanoelectronic technology based High-level synthesis (HLS), and hardware-assisted Digital watermarking. He is currently the Chair of the Technical Committee on Very Large Scale Integration or Technical Committee on VLSI (TCVLSI), IEEE Computer Society (IEEE-CS) since September 2014.[4][5] He is a senior member of both the Institute of Electrical and Electronics Engineers (IEEE) and the Association for Computing Machinery (ACM). He is an inventor of 4 US patents in the areas of his research. Professor Mohanty has published 200 papers and 3 books in the areas of his research.[6][7][8] The scientific articles of Prof. Mohanty are significant contributions to the engineering discipline, scientific community, and society.[9][10][11] He received 2016 PROSE Award for best Textbook in Physical Sciences & Mathematics from the AAP for his book titled "Nanoelectronic Mixed-Signal System Design." His research contributions are well-cited by researchers in different parts of the globe as evident from his Google Scholar metrics.[12] His research has been well-funded by various agencies such as the NSF, the SRC, and the Air Force.[13][14] Professor Mohanty is a very popular professor among students as a professor who cares for them and offers quality materials in a simplified manner.[15]

Notable Scientific Contributions

Contributions to Analog Electronics and Mixed-Signal Circuits

Saraju Mohanty has introduced several novel approaches for ultra-fast design space exploration and optimization of nanoelectronic integrated circuits which can result in energy-efficient, robust, and nanoscale variation-tolerant Analog electronics circuits as well as Mixed-signal integrated circuits. The key feature of these ultra-fast design flows is the need for only two manual layout (or physical design) iterations which saves significant design effort. These ultra-fast design flows rely on accurate metamodels of the analog and mixed-signal circuit components. His research significantly advances the state-of-the art in Design for Excellence (DfX) or Design for X, such as Design for Variability (DfV) and Design for Cost (DfC).[16] The metamodel assisted ultra-fast design optimization flows can perform layout optimization of the components of analog/mixed-signal System on a chip (AMS-SoC) with very minimal design effort. These techniques can lead to over 1,000X speedups. As a specific example, nanoelectronics based phase-locked loop (PLL) which would typically need several days of design cycle for analog simulation with fully modeled parasitics can be optimally designed in less than a day .[17][18] These ultra-fast and accurate methodologies lead to robust and low-cost consumer electronics such as smart mobile phones, making them cheaper and available to larger segments of the population.

Contributions to High-Level Synthesis

Saraju Mohanty is one of the key contributors to nanoscale CMOS or nanoelectronic technology based High-level synthesis (HLS) or architecture-level synthesis.[19][20][21] His nanoelectronic-based High-level synthesis techniques addresses the issue of process variations, the primary issue of nanoelectronic technology, during the high-level synthesis itself before the digital design moves to the detailed and lower levels of design abstractions, such as logic-level or transistor-level.[22] This is a significant effort saver for digital design engineers as the digital design is statistically optimized at the higher-level of abstraction. His HLS techniques produce Register-transfer level descriptions which not only meet traditional specifications, but are also robust against nanoscale process-variations. His HLS techniques are also the first ones to address transient power dissipation or power fluctuation during high-level synthesis, thus distinguishing power-aware design and battery-aware design at the higher levels of design abstractions. This is a very important contribution for digital circuits targeted towards portable AMS-SoCs. Additionally, his research projects in the area of security aware HLS, is one of the upcoming fields in the area of digital integrated circuits and VLSI-CAD. Security aware HLS is an effort to generate datapath designs during HLS that consider security at behavioral level. This research area considers reliability as design specification from the highest design abstraction level. Security aware HLS is important for mission critical applications such as in military/army where hardware security is crucial for trustworthy hardware design. Further, his research contributions in the area of watermarking based HLS for IP core protection is highly significant for consumer electronics and IoT devices. This novel watermarking methodology during HLS protects incurs lower overhead as well as provides robust security than lower level techniques.

Contributions to Digital Watermarking

Saraju Mohanty is a pioneer in hardware-assisted Digital watermarking for real-time copy protection and digital rights management (DRM). He has invented the concept of Secure Digital Camera (SDC) for real-time Digital rights management (DRM) at the source end of the multimedia content.[23][24][25] The SDC has quite diverse applications where still image or video digital cameras are needed, such as secure Digital Video Broadcasting, secure Video Surveillance, electronic passport, and identity card processing. The secure digital camera (SDC) has been well-adopted by various researchers worldwide. In the process it has led to diverse implementations in various platforms by many researchers worldwide.[26][27][28] Professor Mohanty is the designer of the earliest and unique energy-efficient digital watermarking chips.[29] An earliest watermarking chip designed by him can perform invisible digital watermarking at the spatial domain and has capability of both robust and fragile watermarking depending on the choice of the user.[30] A unique digital watermarking chip designed by Professor Mohanty that can perform both visible watermarking and invisible watermarking is the lowest power consuming watermarking chip available at present.

Professional Leadership

Editorial Board

Guest Editor

Conference Steering Committee Member

Conference Chairmanships

Notable Talks

Professional Membership

Awards and Honors

Patents

Saraju Mohanty is an inventor of 4 US patents which have wide applications in Digital watermarking, Digital rights management (DRM), and Mixed-signal integrated circuit design:[77][78][79]

Saraju Mohanty with his best seller nanoelectronic mixed-signal system design book published in 2015 by McGraw-Hill Education.
Saraju Mohanty with his best seller nanoelectronic mixed-signal system design book published in 2015 by McGraw-Hill Education.

Books

Saraju Mohanty has authored or edited 6 books which are widely used as reference text books:

Notable Articles for Advancement of Science and Engineering

  • Everything You wanted to Know about Smart Cities, IEEE Consumer Electronics Magazine, July 2016.
  • Design of a High-Performance System for Secure Image Communication in the Internet of Things, IEEE Access Journal, Volume 4, 2016.
  • Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs, IEEE Transactions on Semiconductor Manufacturing, February 2014.
  • Fast Layout Optimization through Simple Kriging Metamodeling: A Sense Amplifier Case Study, IEEE Transactions on Very Large Scale Integration Systems, April 2014.
  • Variability-Aware Architecture Level Optimization Techniques for Robust Nanoscale Chip Design, Elsevier International Journal on Computers and Electrical Engineering, January 2014.
  • ULS: A Dual-Vth/High-κ Nano-CMOS Universal Level Shifter for System-Level Power Management, ACM Journal on Emerging Technologies in Computing Systems, June 2010.
  • IntellBatt: Toward A Smarter Battery, IEEE Computer, March 2010.
  • Design of Parasitic and Process Variation Aware RF Circuits: A Nano-CMOS VCO Case Study, IEEE Transactions on Very Large Scale Integration Systems, September 2009.
  • A Secure Digital Camera Architecture for Integrated Real-Time Digital Rights Management, Elsevier Journal of Systems Architecture, October–December 2009.
  • Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems, 12th IEEE International Conference on Design Automation and Test in Europe, 2009.
  • Hardware Assisted Watermarking for Multimedia, Elsevier International Journal on Computers and Electrical Engineering, March 2009.
  • IntellBatt: Towards Smarter Battery Design, 45th ACM/IEEE Design Automation Conference, 2008.
  • Invisible Watermarking Based on Creation and Robust Insertion-Extraction of Image Adaptive Watermarks, ACM Transactions on Multimedia Computing, Communications, and Applications, November 2008.
  • VLSI Architecture and Chip for Combined Invisible Robust and Fragile Watermarking, IET Computers & Digital Techniques, September 2007.
  • A Dual Voltage-Frequency VLSI Chip for Image Watermarking in DCT Domain, IEEE Transactions on Circuits and Systems II, May 2006.
  • Physical-Aware Simulated Annealing Optimization of Gate Leakage in Nanoscale Datapath Circuits, 9th IEEE International Conference on Design Automation and Test in Europe, 2006.
  • A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design, IEEE Transactions on Very Large Scale Integration Systems, August 2005.
  • A Framework for Energy and Transient Power Reduction during Behavioral Synthesis, IEEE Transactions on Very Large Scale Integration Systems, June 2004.
  • VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design, 17th International Conference on VLSI Design, 2004.
  • VLSI Implementation of Invisible Digital Watermarking Algorithms Towards the Development of a Secure JPEG Encoder, the IEEE Workshop on Signal Processing System, 2003
  • A DCT Domain Visible Watermarking Technique for Images, 1st IEEE International Conference on Multimedia and Expo, 2000.
  • A Dual Watermarking Technique for Images, 7th ACM International Multimedia Conference, 1999.

Dissertations and Theses Supervised

Doctoral Dissertations Supervised

  1. New Frameworks for Secure Image Communication in the Internet of Things (IoT), University of North Texas, Summer 2016.
  2. Analysis and Optimization of Graphene FET Based Integrated Circuits, University of North Texas, Spring 2016.
  3. Geostatistical Inspired Metamodeling and Optimization of Nanoscale Analog Circuits, University of North Texas, Spring 2014.
  4. Secure and Energy Efficient Execution Frameworks Using Virtualization and Light-Weight Cryptographic Components, University of North Texas, Summer 2014.
  5. Layout-Accurate Ultra-Fast System Level Design Exploration Through Verilog-AMS, University of North Texas, Spring 2013.
  6. Metamodeling-Based Fast Optimization of Nanoscale AMS-SoCs, University of North Texas , Spring 2010.
  7. Process-Voltage-Temperature Aware Nanoscale Circuit Optimization, University of North Texas, Fall 2010.
  8. Variability Aware Low-Power Techniques for Nanoscale Mixed-Signal Circuits, University of North Texas, Spring 2009.

Masters Theses Supervised

  1. Simulink Based Modeling of A Multi Global Navigation Satellite System, University of North Texas, Summer 2016.
  2. Exploring Analog and Digital Design using the Open-source Electric VLSI Design System, University of North Texas, Spring 2016.
  3. Simulink Based Design and Implementation of a Solar Power Based Mobile Charger, University of North Texas, Fall 2015.
  4. Comparative Analysis and Implementation of High Data Rate Wireless Sensor Network Simulation Frameworks, University of North Texas, Fall 2015.
  5. General Purpose Computing in GPU - A Watermarking Case Study, University of North Texas, Summer 2014.
  6. Exploring Memristor Based Analog Design in Simscape, University of North Texas, Spring 2013.
  7. Rapid Prototyping and Design of a Fast Random Number Generator, University of North Texas, Spring 2012.
  8. OTA-Quadrotor: An Object-Tracking Quadrotor for Real-Time Detection and Recognition, University of North Texas, Spring 2012.
  9. Exploring Process-Variation Tolerant Design of Nanoscale Sense Amplifier Circuits, University of North Texas, Fall 2010.
  10. Software and Hardware in the Loop Modeling of an Audio Watermarking Algorithm, University of North Texas, Fall 2010.
  11. A New N-Way Reconfigurable Data Cache Architecture for Embedded Systems, University of North Texas, Fall 2009.
  12. A Verilog 8051 Softcore for FPGA Applications, University of North Texas, Spring 2009.
  13. Region Aware DCT Domain Invisible Robust Blind Watermarking for Color Images, University of North Texas, Fall 2008.
  14. Hardware Software Co-Design of a JPEG2000 Watermarking Encoder, University of North Texas, Fall 2008.
  15. A CAM based High-Performance Classifier-Scheduler for a Video Network Processor, University of North Texas, Spring 2008.
  16. Occlusion Tolerant Object Recognition Methods for Video Surveillance and Tracking of Moving Civilian Vehicles, University of North Texas, Fall 2007.
  17. A Nano-CMOS Based Universal Voltage Level Converter for Multi-VDD SoCs, University of North Texas, Spring 2007, Major Professor.
  18. CMOS Active Pixel Sensors for Digital Cameras: Current State-of-the-Art, University of North Texas, Spring 2007, Major Professor.
  19. FPGA Prototyping of a Watermarking Algorithm for MPEG-4, University of North Texas, Spring 2007.
  20. Design and Optimization of Components in a 45nm CMOS Phase Locked Loop, University of North Texas, Fall 2006.
  21. Comparison and Evaluation of Existing Analog Circuit Simulators Through a Sigma-Delta Modulator, University of North Texas, Fall 2006.
  22. VLSI Architecture and FPGA Prototyping of a Secure Digital Camera for Biometric Application, University of North Texas, Summer 2006.
  23. Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Datapath Circuits, University of North Texas, Spring 2006.
  24. A Dual Dielectric Approach for Performance Aware Reduction of Gate Leakage in Combinational Circuits, University of North Texas, Spring 2006.
  25. VLSI Implementation of Invisible Robust/Fragile Digital Watermarking Algorithms, Manipal Centre for Information Science, Manipal Academy of Higher Education, India, Spring 2004.

Education

Saraju Mohanty started his schooling at Lodhachua, Nayagarh, Odisha. He did his grade 3 to grade 5 studies at the Badagada Primary School at Bhubaneswar. After that he did his high school education from grade 7 to grade 10 at Badagada Government High School, Bhubaneswar. After graduating from Badagada Government High School, Bhubaneswar in 1988, Mohanty completed a 10+2 Science degree from the Rajdhani College, Bhubaneswar in 1990. Whilst at high school he was a quite active and recognized member of The Bharat Scouts and Guides. He received his bachelor's degree (with Honors) in electrical engineering from the College of Engineering and Technology, Bhubaneswar, Orissa University of Agriculture and Technology, in 1995. He received a number of scholarships throughout his undergraduate and graduate studies.

In 1999 Mohanty completed a master's degree in engineering in Systems Science and Automation from the Indian Institute of Science in Bangalore, India. His master's thesis mentors were Professor K. R. Ramakrishnan[90] and Professor Mohan S. Kankanhalli[91] with whom he co-authored the first peer-reviewed paper of his life.[92] Mohanty earned a Ph.D. in Computer engineering from the University of South Florida (USF) in 2003. His Ph.D. mentor was Professor N. Ranganathan (IEEE Fellow and AAAS Fellow).[93][94][95]

Personal life

Professor Mohanty was born in Lodhachua, Ranpur, in the state of Odisha, India near the capital city of Bhubaneswar. He lived in Bhubaneswar until he completed his undergraduate education from College of Engineering and Technology, Bhubaneswar. In 1997, he moved to Bangalore for his Masters studies at Indian Institute of Science (IISc) Bangalore. After completing the Masters education, he moved to United States for his doctoral education. In 2003, he completed his Ph.D. It is during while doing his doctoral studies that he met his wife Dr. Uma Choppali. Dr. Uma Choppali had her Masters in Physics from the Indian Institute of Technology Bombay, India. She was enrolled in Ph.D. (Physics) at the University of South Florida at Tampa, Florida, when they met. They got married in 2003 at Tampa, Florida. Dr. Uma Choppali completed her Ph.D. in Materials Science and Engineering from the University of North Texas at Denton.

References

  1. ↑ The University of North Texas, Dept. of Computer Science and Engineering, NanoSystem Design Laboratory, http://nsdl.cse.unt.edu/
  2. ↑ The University of North Texas, Dept. of Computer Science and Engineering, http://www.cse.unt.edu/site/node/91
  3. ↑ Research Interests, Prof. Saraju Mohanty, http://www.cse.unt.edu/~smohanty/Research.html
  4. ↑ Dr. Saraju Mohanty Serves as the Chair of the Technical Committee on Very Large Scale Integration (TCVLSI), https://facultysuccess.unt.edu/dr-saraju-mohanty-serves-chair-technical-committee-very-large-scale-integration-tcvlsi
  5. ↑ Technical Committee on VLSI, http://www.computer.org/portal/web/tandc/tcvlsi
  6. ↑ ResearchGate - Saraju Mohanty, http://www.researchgate.net/profile/Saraju_Mohanty
  7. ↑ Google Scholar List - Saraju Mohanty, https://scholar.google.com/scholar?hl=en&q=saraju+mohanty
  8. ↑ DBLP - Saraju Mohanty, http://dblp.uni-trier.de/pers/hd/m/Mohanty:Saraju_P=.html
  9. ↑ Interviews: Energy Efficient Buildings & Communities Workshop, University of Tartu, Estonia, http://www.uttv.ee/naita?id=17227&keel=eng
  10. ↑ Less time on the charger, http://www.unt.edu/features/mohanty/index.htm
  11. ↑ US Department of Energy, E-print Network, Computer Technologies and Information Sciences, Preprints Provided by Individual Scientists, http://www.osti.gov/eprints/pathways/computertechM.shtml
  12. ↑ Google Scholar Citation - Saraju P. Mohanty, https://scholar.google.com/citations?user=G0uvNwsAAAAJ&hl=en
  13. ↑ At one-billionth of a meter, scientists create on the cutting edge, UNT Research Magazine, Volume 20, 2011, http://www.unt.edu/untresearch/2010-2011/advancing-nanotechnology.htm
  14. ↑ UNT researcher works to make energy-efficient chips, August 20, 2009, https://news.unt.edu/news-releases/unt-researcher-works-make-energy-efficient-chips
  15. ↑ Rate my Professors, Saraju Mohanty, Professor in the Computer Science department, University of North Texas, Denton, TX, http://www.ratemyprofessors.com/ShowRatings.jsp?tid=1664572
  16. ↑ DFX for Nanoelectronic Embedded Systems, Keynote Address at First IEEE Sponsored International Conference on Control, Automation, Robotics and Embedded System, CARE-2013, http://care.iiitdmj.ac.in/Keynote_Speakers.html.
  17. ↑ Mohanty, S. P.; Kougianos, E. (2014). "Polynomial Metamodel Based Fast Optimization of Nano-CMOS Oscillator Circuits". Analog Integrated Circuits and Signal Processing Journal. 79 (3): 437–453. doi:10.1007/s10470-014-0284-2.
  18. ↑ Mohanty, S. P.; Kougianos, E. (2014). "Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs". IEEE Transactions on Semiconductor Manufacturing. 27 (1): 22–31. doi:10.1109/tsm.2013.2291112.
  19. ↑ Saraju Mohanty and Elias Kougianos, "Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis", in Proceedings of the 20th International Conference on VLSI Design, pp. 577-582, 2007.
  20. ↑ Mohanty, S. P.; Gomathisankaran, M.; Kougianos, E. (2014). "Variability-Aware Architecture Level Optimization Techniques for Robust Nanoscale Chip Design". Elsevier Computers and Electrical Engineering Journal. 40 (1): 168–193. doi:10.1016/j.compeleceng.2013.11.026.
  21. ↑ Chen, Y.; Wang, Y.; Takach, A.; Xie, Y. "Parametric Yield Driven Resource Binding in High-Level Synthesis with Multi-Vth Vdd Library and Device Sizing". Journal of Electrical and Computer Engineering. 2012: 105250.
  22. ↑ "Unified Challenges in Nano-CMOS High-Level Synthesis", Invited Talk, 22nd IEEE International Conference on VLSI Design, 2009.
  23. ↑ Secure digital camera#Secure digital camera
  24. ↑ Mohanty, Saraju. "A Secure Digital Camera Architecture for Integrated Real-Time Digital Rights Management". Elsevier Journal of Systems Architecture. 55 (10-12): 468–480. doi:10.1016/j.sysarc.2009.09.005.
  25. ↑ S. P. Mohanty, O. B. Adamo, and E. Kougianos, "VLSI Architecture of an Invisible Watermarking Unit for a Biometric-Based Security System in a Digital Camera", in Proceedings of the 25th IEEE International Conference on Consumer Electronics, pp. 485-486, 2007.
  26. ↑ Thomas Winkler, Adam Erdelyi, and Bernhard Rinner, "TrustEYE M4: Protecting the Sensor--not the Camera", in Proceedings of the International Conference on Advanced Video and Signal Based Surveillance, 2014.
  27. ↑ Roy, S. D.; Li, Xin; Shoshan, Y.; Fish, A.; Yadid-Pecht, O. (2013). "Hardware Implementation of a Digital Watermarking System for Video Authentication". IEEE Transactions on Circuits and Systems for Video Technology. 23 (2): 289–301. doi:10.1109/tcsvt.2012.2203738.
  28. ↑ Yen, C. -T.; Wu, T. -C.; Guo, M. -H.; Yang, C. -K.; Chao, H. -C. (2010). "Digital product transaction mechanism for electronic auction environment". IET Information Security. 4 (4): 248–257. doi:10.1049/iet-ifs.2009.0250.
  29. ↑ S. P. Mohanty, N. Ranganathan, and R. K. Namballa, "VLSI Implementation of Invisible Digital Watermarking Algorithms Towards the Development of a Secure JPEG Encoder", in Proceedings of the IEEE Workshop on Signal Processing System, pp. 183-188, 2003.
  30. ↑ S. P. Mohanty, N. Ranganathan, and K. Balakrishnan, "Design of a Low Power Image Watermarking Encoder using Dual Voltage and Frequency", in Proceedings of the 18th IEEE International Conference on VLSI Design, pp. 153-158, 2005.
  31. 1 2 3 UNT Professor Receives Editorial Appointments, Recognition, http://engineering.unt.edu/unt-professor-receives-editorial-appointments-recognition
  32. ↑ IEEE Consumer Electronics Magazine Editorial Board, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7450780
  33. ↑ IEEE Consumer Electronics Magazine, http://ieeexplore.ieee.org/xpl/aboutJournal.jsp?punumber=5962380
  34. ↑ IEEE Consumer Electronics Magazine, http://cesoc.ieee.org/publications/ce-magazine.html
  35. ↑ VLSI Circuits and Systems Letter (VCAL) -- Editorial Board, https://www.computer.org/web/tcvlsi/editorial-board
  36. ↑ Editorial Board, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), http://ieee-ceda.org/publications/tcad/editorial-board
  37. ↑ Editorial Board, ACM Journal on Emerging Technologies in Computing Systems (JETC), http://jetc.acm.org/editorial_board.cfm
  38. ↑ IEEE Consumer Electronics Magazine (MCE) -- IEEE Consumer Electronics Magazine Editorial Board Member Roster, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7308143
  39. ↑ IET Circuits, Devices and Systems (CDS) -- Editorial board, http://digital-library.theiet.org/journals/iet-cds/editorial-board
  40. ↑ Integration, the VLSI Journal -- Editorial Board, http://www.journals.elsevier.com/integration-the-vlsi-journal/editorial-board/
  41. ↑ ASP Journal of Low Power Electronics (JOLPE) -- Editorial Board, http://www.aspbs.com/jolpe/editorial_jolpe.htm
  42. ↑ Special Issue on Circuit and System Design Automation for Internet of Things, https://mc.manuscriptcentral.com/societyimages/tcad/CFP_Special-Circuit%20and%20System%20Design%20Automation%20for%20Internet%20of%20Things.pdf
  43. ↑ IEEE Transactions on Nanotechnology (TNANO) -- Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing, http://sites.ieee.org/tnano/2015/12/special-issue-ion-processing/
  44. ↑ ACM Journal on Emerging Technologies in Computing Systems (JETC) -- Nanoelectronic Circuit and System Design Methods for Mobile Computing Era, http://jetc.acm.org/pdf/ACM-JETC_SI_NanoMobi_CFP.pdf
  45. ↑ Elsevier The VLSI Integration Journal (Integration) -- Hardware Assisted Techniques for IoT and Bigdata Applications, http://www.journals.elsevier.com/integration-the-vlsi-journal/call-for-papers/special-issue-on-hardware-assisted-techniques-for-iot/
  46. ↑ IEEE Access -- Security and Reliability Aware System Design for Mobile Computing Systems, http://www.ieee.org/publications_standards/publications/ieee_access/security_reliability.pdf
  47. ↑ IEEE Transactions on Emerging Topics in Computing (TETC) -- Circuit and System Design Methodologies for Emerging Technologies, Vol. 3, No. 4, October–December 2015, http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6245516
  48. ↑ Springer Circuits, Systems, and Signal Processing Journal (CSSP), Volume 32, Issue 6, December 2013, http://link.springer.com/journal/34/32/6/page/1
  49. ↑ IET Circuits, Devices, & Systems Journal (CDS), Volume 7, issue 5, September 2013, http://digital-library.theiet.org/content/journals/iet-cds/7/5#headline1
  50. ↑ ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 8, Issue 3, August 2012, http://portalparts.acm.org/2290000/2287696/fm/frontmatter.pdf?ip=173.74.56.32&CFID=735311818&CFTOKEN=90085137
  51. ↑ ASP Journal of Low Power Electronics (JOLPE), Volume 8, Issue 3, June 2012, http://www.aspbs.com/jolpe/contents_jolpe2012.htm#v8n3
  52. ↑ Elsevier International Journal on Computers and Electrical Engineering, Volume 35, Issue 2, March 2009, http://www.sciencedirect.com/science/journal/00457906/35/2
  53. ↑ IEEE Computer Society Annual Symposium on VLSI (ISVLSI), http://www.isvlsi.org
  54. ↑ IEEE International Symposium on Nanoelectronic and Information Systems (IEEE-iNIS), http://www.ieee-inis.org/
  55. ↑ International Conference on Information Technology (ICIT), http://www.oits-icit.org
  56. ↑ Orissa Information Technology Society, http://www.oits.org
  57. ↑ IEEE-iNIS Steering Committee, http://jnana-erebus.org/inis/current/#team
  58. ↑ ISVLSI Steering Committee, http://www.eng.ucy.ac.cy/theocharides/isvlsi17/committee.html
  59. ↑ International Symposium on Nanoelectronic and Information Systems (IEEE iNIS 2015), 21–23 December 2015, Indore, India, http://www.globaleventslist.elsevier.com/events/2015/12/international-symposium-on-nanoelectronic-and-information-systems-inis/
  60. ↑ Computer Science and Engineering Researcher Chairs International Symposium, August 2015, http://engineering.unt.edu/computer-science-and-engineering-researcher-chairs-international-symposium
  61. ↑ IEEE’s first intl symposium on iNIS to be held in City, Aug 17, 2015, http://www.freepressjournal.in/ieees-first-intl-symposium-on-inis-to-be-held-in-city/
  62. ↑ A student research symposium was organised by ISTE-Silicon Student chapter - See more at: http://www.orissadiary.com/CurrentNews.asp?id=56591#sthash.iP2IFtmy.dpuf
  63. ↑ The International Conference on Information Technology (ICIT), http://www.oits-icit.org
  64. ↑ Orissa Information Technology Society (OITS), http://www.oits.org/
  65. ↑ The 22nd International Conference on VLSI Design -- Unified Challenges in Nano-CMOS High-Level Synthesis, 2009, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4749726&newsearch=true&queryText=Unified%20Challenges%20in%20Nano-CMOS%20High-Level%20Synthesis
  66. ↑ Technical & Conferences Activities Board -- Technical Committees -- Technical Committee on VLSI, http://www.computer.org/web/tandc/tcvlsi
  67. ↑ Dr. Saraju Mohanty Serves as the Chair of the Technical Committee on Very Large Scale Integration (TCVLSI), http://www.cse.unt.edu/site/node/678
  68. ↑ 2016 PROSE Award Winners, https://proseawards.com/winners/2016-award-winners/#body
  69. ↑ Saraju Mohanty wins McGraw-Hill textbook award, https://facultysuccess.unt.edu/faculty-awards/saraju-mohanty-wins-mcgraw-hill-textbook-award
  70. ↑ Engineering Professor Receives Awards, http://engineering.unt.edu/engineering-professor-receives-awards
  71. ↑ Salute to Faculty Excellence 2016 Winners, http://facultysuccess.unt.edu/salute-faculty-excellence-2016-winners-0
  72. ↑ ISVLSI 2015, http://www.eng.ucy.ac.cy/theocharides/isvlsi15/
  73. ↑ USF Notable Alumnus, Bulls to Brag About, USF Alumni Association Website.
  74. ↑ Indian Institute of Science Notable Alumnus, Indian Institute of Science.
  75. ↑ College of Engineering and Technology, Bhubaneswar Notable Alumnus, College of Engineering and Technology, Bhubaneswar
  76. ↑ CET Rising, Interviewed: Mr. Saraju Mohanty, Interview Taken by: Trishala Mishra, Saturday, 29 August 2015, http://rising.cetb.in/2015/08/interviewed-mr-saraju-mohanty.html
  77. ↑ Engineering Professors Awarded Multiple Patents to Innovate Integrated Circuit Design, UNT Faculty Success Newsletter, October 2015, https://facultysuccess.unt.edu/unt-faculty-newsletter-october-2015-edition.
  78. ↑ Researchers Receive Patent for a Method for Designing Complex, Mixed-signal Circuits, October 2015, http://engineering.unt.edu/researchers-receive-patent-method-designing-complex-mixed-signal-circuits
  79. ↑ Researchers Awarded Patent for Method to Innovate Mixed-signal Integrated Circuit Design, May 2015, http://engineering.unt.edu/researchers-awarded-patent-method-innovate-mixed-signal-integrated-circuit-design
  80. ↑ Methodology for Nanoscale Technology based Mixed-Signal System Design, US Patent Number: 9,053,276, Issued on: 9th June 2015 http://assignment.uspto.gov/#/assignment?id=30967-123&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
  81. ↑ Intelligent Metamodel Integrated Verilog-AMS for Fast and Accurate Analog Block Design Exploration, US Patent Number: 9,026,964, Issued on: 5th May 2015 http://assignment.uspto.gov/#/assignment?id=32972-875&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
  82. ↑ Apparatus and Method for Transmitting Secure and/or Copyrighted Digital Video Broadcasting Data Over Internet Protocol Network, US Patent Number: 8,423,778, Issued on: 16th Apr 2013 http://assignment.uspto.gov/#/assignment?id=22252-43&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
  83. ↑ Methods and Devices for Enrollment and Verification of Biometric Information in Identification Documents, US Patent Number: 8,058,972, Issued on: 15th Nov 2011 http://assignment.uspto.gov/#/assignment?id=21372-691&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
  84. ↑ http://www.mhprofessional.com/product.php?isbn=0071825711
  85. ↑ Saraju Mohanty wins McGraw-Hill textbook award, http://www.cse.unt.edu/site/node/677
  86. ↑ http://www.theiet.org/resources/books/circuits/nano-cmos-post-cmos-vol1.cfm
  87. ↑ http://www.theiet.org/resources/books/circuits/Ncmosvol2.cfm
  88. ↑ http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4614-08178
  89. ↑ http://www.springer.com/engineering/circuits+%26+systems/book/978-0-387-76473-3
  90. ↑ S. P. Mohanty, "Watermarking of Digital Images", Master of Engineering in System Science and Automation Thesis, Indian Institute of Science, Bangalore, January 1999, http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.10.1673&rep=rep1&type=pdf
  91. ↑ "Past Postdocs and Graduated Students". Retrieved 8 August 2016.
  92. ↑ S. P. Mohanty, K. R. Ramakrishnan, and M. S. Kanakanhalli, "A Dual Watermarking Technique for Images", in Proceedings of the 7th ACM International Multimedia Conference (ACMMM) (Vol. 2), pp.49-51, 1999.
  93. ↑ S. P. Mohanty, "Energy and Transient Power Minimization During Behavioral Synthesis", Ph.D. Dissertation, Department of Computer Science and Engineering, University of South Florida, 2003, http://etd.fcla.edu/SF/SFE0000129/SarajuDissertationFinal.pdf
  94. ↑ Computer Science Tree, N. Ranganathan, University of South Florida, http://academictree.org/computerscience/tree.php?pid=416222
  95. ↑ Nagarajan “Ranga” Ranganathan, Department of Computer Science and Engineering, University of South Florida, Tampa, FL 33620,http://www.usf.edu/engineering/cse/documents/ranganathan-cv.pdf
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