ZEBRA (computer)

The ZEBRA (Zeer Eenvoudige Binaire Reken Automaat translated Very Simple Binary Automatic Calculator) was one of the first computers to be designed in the Netherlands, (the first one was the "ARRA") and one of the first Dutch computers to be commercially available. It was designed by Willem van der Poel of the Netherlands Post, Telegraph and Telephone, and first delivered in 1958. The production run consisted of fifty-five machines, manufactured and marketed by the British company Standard Telephones and Cables, Ltd.

The ZEBRA was a binary, two-address machine with a 33-bit word length. Storage was provided by a magnetic drum memory holding 8K words; accumulators were also implemented as recirculating drum tracks in a manner similar to that used in the Bendix G-15. Peripherals included paper tape reader and punch, and teleprinter.

Programming

The ZEBRA instruction word consists of a 13-bit drum address, a five-bit register (or I/O) address, and a 15-bit operation field. Each bit of the operation field had a distinct meaning and could be used in nearly any combination, leading to many elegant tricks that today might be considered the domain of microprogramming. Some bits made an instruction conditional on the accumulator state, as with the Zuse Z22 or Electrologica X1. Multiplication, division, square root, as well as all floating-point operations, were performed by subroutines, using the underlying serial computer ALU primitives add, subtract, shift right, shift left, and increment. Programming aids included the Normal Code (assembler), trace utility, a floating point interpretive system, the Simple Code, the Matrix Interpretive Scheme, and an Algol compiler.

Since a magnetic drum does not support random access, some time is lost waiting for an instruction or piece of data become available. In a poorly written program, the average wait time could be half the drum rotation time, but there were ways to reduce this. A notable feature of the ZEBRA was a meter that measured how much of the machine's time was spent in non-wait states; this was called the "efficiency meter." When running the floating-point interpretive system, the efficiency meter tended to show around 50%, but if prospective customers were visiting, a more efficient program could be loaded for demonstration purposes.

External links

CPU technologies

Architecture	Von Neumann Harvard (Modified) Dataflow TTA

Instruction set	ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison

Word size	1-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable

Execution	Instruction pipelining Bubble Operand forwarding Out-of-order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards

Parallel level	Bit Bit-serial Word Instruction Scalar Superscalar Task Thread Process Data Vector Memory

Multithreading	Temporal Simultaneous Preemptive Cooperative

Flynn's taxonomy	SISD SIMD MISD MIMD SPMD Addressing mode

Core count	Single-core processor Multi-core processor Manycore processor

Types	Digital signal processor (DSP) GPGPU Microcontroller Physics processing unit System on a chip (SoC) Cellular

Components	Address generation unit (AGU) Arithmetic logic unit (ALU) Barrel shifter Floating-point unit (FPU) Back-side bus Multiplexer Demultiplexer Registers Memory management unit (MMU) Translation lookaside buffer (TLB) Cache Register file Microcode Control unit Clock rate

Power management	APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating

Hardware security	Non-executable memory (NX bit) Bounds checking (Intel MPX) Hardware restriction (firmware) Software Guard Extensions (Intel SGX) Trusted Execution Technology Secure cryptoprocessor Hardware security module Hengzhi chip

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