OpenSPARC
OpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level (RTL) Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor. On March 21, 2006, Sun released the source code to the T1 IP core under the GNU General Public License. The full OpenSPARC T1 system consists of 8 cores, each one capable to execute 4 threads concurrently, for a total of 32 threads. Each core executes instruction in order and its logic is split among 6 pipeline stages.
On December 11, 2007, Sun also made the UltraSPARC T2 processor's RTL available via the OpenSPARC project.[1] OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads.
See also
- LEON
- S1 Core (a derived single-core implementation)
- SPARC (Scalable Processor ARChitecture)
- Field-programmable gate array
References
- ↑ "Sun Accelerates Grown of UltraSPARC CMT Eco System". Sun Microsystems. 2007-12-11. Retrieved 2008-05-23.
External links
- OpenSPARC site
- T1 Specifications and Source code
- T2 Specifications and Source code
- SPARC: Open Source at DMOZ
- Open Source Semiconductor Core Licensing, 25 Harvard Journal of Law & Technology 131 (2011) Article analyzing the law, technology and business of open source semiconductor cores
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