ARM Cortex-M

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings. The cores are intended for microcontroller use, and consist of the Cortex-M0, M0+, M1, M3, M4, M7, M23, M33.^{[1][2][3][4][5]}

Overview

Announced
Year	Core
2004	Cortex-M3
2007	Cortex-M1
2009	Cortex-M0
2010	Cortex-M4
2012	Cortex-M0+
2014	Cortex-M7
2016	Cortex-M23
2016	Cortex-M33

ARM license

ARM Holdings neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To all licensees, ARM provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU.

Silicon customization

Integrated device manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions, optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.

Some of the most important options for the Cortex-M cores are:

• SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an additional configurable priority SysTick interrupt.^[6][7][8] Though the SysTick timer is optional, it's rare to see a Cortex-M microcontroller without it.
• Bit-banding: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bitband region. This allows every individual bit in the bit-banding region to be directly accessible from a word-aligned address, and individual bits to be toggled from C/C++ without performing a read-modify-write sequence of instructions.^[6][7][8]
• Memory Protection Unit (MPU): Provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to eight different regions, each of which can be split into a further eight equal-size sub-regions.^[6][7][8]

ARM Cortex-M optional components^[6][7]

ARM Cortex-M	SysTick Timer	Bit- banding	Memory Protection Unit (MPU)	Tightly-Coupled Memory (TCM)	CPU cache	Memory architecture	ARM architecture
Cortex-M0[1]	Optional*	Optional[9]	No	No	No[10]	Von Neumann	ARMv6-M
Cortex-M0+[2]	Optional*	Optional[9]	Optional (8)	No	No	Von Neumann	ARMv6-M
Cortex-M1[3]	Optional	Optional	No	Optional	No	Von Neumann	ARMv6-M
Cortex-M3[4]	Yes	Optional*	Optional (8)	No	No	Harvard	ARMv7-M
Cortex-M4[5]	Yes	Optional*	Optional (8)	No	Possible[11]	Harvard	ARMv7E-M
Cortex-M7	Yes	No	Optional (8 or 16)	Optional	Optional	Harvard	ARMv7E-M

• Note: Most Cortex-M3 and M4 chips have bit-banding and MPU. The bit-banding option can be added to the Cortex-M0 / M0+ using the Cortex-M System Design Kit.^[9]
• Note: Software should validate the existence of a feature before attempting to use it.^[8]

Additional silicon options:^[6][7]

• Data endianness: Little-endian or big-endian. Unlike legacy ARM cores, the Cortex-M is permanently fixed in silicon as one of these choices.
• Interrupts: 1 to 32 (Cortex-M0/M0+/M1), 1 to 240 (Cortex-M3/M4/M7).
• Wake-up interrupt controller: Optional.
• Vector Table Offset Register: Optional.
• Instruction fetch width: 16-bit only, or mostly 32-bit.
• User/privilege support: Optional.
• Reset all registers: Optional.
• Single-cycle I/O port: Optional.
• Debug Access Port (DAP): Optional.
• Halting debug support: Optional.
• Number of watchpoint comparators: 0 to 2 (Cortex M0/M0+/M1), 0 to 4 (Cortex-M3/M4/M7).
• Number of breakpoint comparators: 0 to 4 (Cortex M0/M0+/M1), 0 to 8 (Cortex-M3/M4/M7).

Instruction sets

The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture,^[6] the Cortex-M3 implements the ARMv7-M architecture,^[7] and the Cortex-M4 / M7 implements the ARMv7E-M architecture.^[7] The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / M0+ / M1 can execute without modification on the Cortex-M3 / M4 / M7. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / M7.^[6][7] Only Thumb and Thumb-2 instruction sets are supported in Cortex-M architectures, but the legacy 32-bit ARM instruction set isn't supported.

All six Cortex-M cores implement a common subset of instructions that consists of most Thumb, some Thumb-2, including a 32-bit result multiply. The Cortex-M0 / M0+ / M1 were designed to create the smallest silicon die, thus having the fewest instructions of the Cortex-M family.

The Cortex-M0 / M0+ / M1 include Thumb instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture. The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR). The Cortex-M3 / M4 / M7 have all base Thumb and Thumb-2 instructions. The Cortex-M3 adds 3 Thumb instructions, all Thumb-2 instructions, hardware divide, and saturation arithmetic instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point unit (VFPv4-SP). The Cortex-M7 adds an optional double-precision FPU (VFPv5).^[6][7]

ARM Cortex-M instruction variations^[6][7]

ARM Cortex-M	Thumb	Thumb-2	Hardware multiply	Hardware divide	Saturated math	DSP extensions	Floating-Point Unit (FPU)	ARM architecture
Cortex-M0[1]	Most	Some	32-bit result	No	No	No	No	ARMv6-M
Cortex-M0+[2]	Most	Some	32-bit result	No	No	No	No	ARMv6-M
Cortex-M1[3]	Most	Some	32-bit result	No	No	No	No	ARMv6-M
Cortex-M3[4]	Entire	Entire	32 or 64-bit result	Yes	Yes	No	No	ARMv7-M
Cortex-M4[5]	Entire	Entire	32 or 64-bit result	Yes	Yes	Yes	Optional: SP	ARMv7E-M
Cortex-M7	Entire	Entire	32 or 64-bit result	Yes	Yes	Yes	Optional: SP or SP & DP	ARMv7E-M

• Note: The Cortex-M0 / M0+ / M1 doesn't include these 16-bit Thumb instructions: CBZ, CBNZ, IT.^[6][7]
• Note: The Cortex-M0 / M0+ / M1 only include these 32-bit Thumb-2 instructions: BL, DMB, DSB, ISB, MRS, MSR.^[6][7]
• Note: The Cortex-M0 / M0+ / M1 only has 32-bit multiply instructions with a lower-32-bit result (32bit × 32bit = lower 32bit), where as the Cortex-M3 / M4 / M7 includes additional 32-bit multiply instructions with 64-bit results (32bit × 32bit = 64bit). The Cortex-M4 / M7 also include DSP instructions for (16bit × 16bit = 32bit), (32bit × 16bit = upper 32bit), (32bit × 32bit = upper 32bit) multiplications. If a smaller silicon die is required, the Cortex-M0 / M0+ / M1 has an option to be a much slower instruction, though it is rarely implemented in the M0 or M0+.^[6][7]
• Note: The Cortex-M4 has a silicon FPU option (VFPv4-SP) of single-precision (SP), which is known as a Cortex-M4F. The Cortex-M7 has silicon FPU options (VFPv5) of single-precision (SP), or both single-precision (SP) and double-precision (DP). If the Cortex-M4 or M7 has a FPU, then it is known as the Cortex-M4F or Cortex-M7F.^[6][7]
• Note: The Cortex-M series includes three new 16-bit Thumb instructions for sleep mode: SEV, WFE, WFI.

ARM Cortex-M instruction groups

Instructions	Instruction size	Cortex M0	Cortex M0+	Cortex M1	Cortex M3	Cortex M4	Cortex M7
ADC, ADD, ADR, AND, ASR, B, BIC, BKPT, BLX, BX, CMN, CMP, CPS, EOR, LDM, LDR, LDRB, LDRH, LDRSB, LDRSH, LSL, LSR, MOV, MUL, MVN, NOP, ORR, POP, PUSH, REV, REV16, REVSH, ROR, RSB, SBC, SEV, STM, STMIA, STR, STRB, STRH, SUB, SVC, SXTB, SXTH, TST, UXTB, UXTH, WFE, WFI, YIELD	16-bit	Yes	Yes	Yes	Yes	Yes	Yes
BL, DMB, DSB, ISB, MRS, MSR	32-bit	Yes	Yes	Yes	Yes	Yes	Yes
CBNZ, CBZ, IT	16-bit	No	No	No	Yes	Yes	Yes
ADC, ADD, ADR, AND, ASR, B, BFC, BFI, BIC, CDP, CLREX, CLZ, CMN, CMP, DBG, EOR, LDC, LDMA, LDMDB, LDR, LDRB, LDRBT, LDRD, LDREX, LDREXB, LDREXH, LDRH, LDRHT, LDRSB, LDRSBT, LDRSHT, LDRSH, LDRT, MCR, LSL, LSR, MLS, MCRR, MLA, MOV, MOVT, MRC, MRRC, MUL, MVN, NOP, ORN, ORR, PLD, PLDW, PLI, POP, PUSH, RBIT, REV, REV16, REVSH, ROR, RRX, RSB, SBC, SBFX, SDIV, SEV, SMLAL, SMULL, SSAT, STC, STMDB, STR, STRB, STRBT, STRD, STREX, STREXB, STREXH, STRH, STRHT, STRT, SUB, SXTB, SXTH, TBB, TBH, TEQ, TST, UBFX, UDIV, UMLAL, UMULL, USAT, UXTB, UXTH, WFE, WFI, YIELD	32-bit	No	No	No	Yes	Yes	Yes
PKH, QADD, QADD16, QADD8, QASX, QDADD, QDSUB, QSAX, QSUB, QSUB16, QSUB8, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSAX, SHSUB16, SHSUB8, SMLABB, SMLABT, SMLATB, SMLATT, SMLAD, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, SMLAWB, SMLAWT, SMLSD, SMLSLD, SMMLA, SMMLS, SMMUL, SMUAD, SMULBB, SMULBT, SMULTT, SMULTB, SMULWT, SMULWB, SMUSD, SSAT16, SSAX, SSUB16, SSUB8, SXTAB, SXTAB16, SXTAH, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSAX, UHSUB16, UHSUB8, UMAAL, UQADD16, UQADD8, UQASX, UQSAX, UQSUB16, UQSUB8, USAD8, USADA8, USAT16, USAX, USUB16, USUB8, UXTAB, UXTAB16, UXTAH, UXTB16	32-bit	No	No	No	No	Yes	Yes
VABS, VADD, VCMP, VCMPE, VCVT, VCVTR, VDIV, VLDM, VLDR, VMLA, VMLS, VMOV, VMRS, VMSR, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VPOP, VPUSH, VSQRT, VSTM, VSTR, VSUB	32-bit	No	No	No	No	Optional SP FPU	Optional SP FPU
VCVTA, VCVTM, VCVTN, VCVTP, VMAXNM, VMINNM, VRINTA, VRINTM, VRINTN, VRINTP, VRINTR, VRINTX, VRINTZ, VSEL	32-bit	No	No	No	No	No	Optional DP FPU

• Note: The single-precision (SP) FPU instructions are valid in the Cortex-M4/M7 only when the SP FPU option exists in the silicon.
• Note: The double-precision (DP) FPU instructions are valid in the Cortex-M7 only when the DP FPU option exists in the silicon.

ARM deprecations

The ARM architecture for ARM Cortex-M series removed some features from older legacy cores:^[6][7]

• The 32-bit ARM instruction set is not included in Cortex-M cores.
• Endianness is chosen at silicon implementation in Cortex-M cores. Legacy cores allowed "on-the-fly" changing of the data endian mode.
• Co-processors aren't supported on Cortex-M cores.

The capabilities of the 32-bit ARM instruction set is duplicated in many way by the Thumb and Thumb-2 instruction sets, but some ARM features don't have a similar feature:

• The SWP and SWPB (swap) ARM instructions don't have a similar feature in Cortex-M.

The 16-bit Thumb instruction set has evolved over time since it was first released in the legacy ARM7T cores with the ARMv4T architecture. New Thumb instructions were added as each legacy ARMv5 / ARMv6 / ARMv6T2 architectures were released. Some 16-bit Thumb instructions were removed from the Cortex-M cores:

• "BLX <immediate>" instruction doesn't exist because it was used to switch from Thumb to ARM instruction set. The "BLX <register>" instruction is still available in the Cortex-M.
• CPSIE and CPSID also don't exist because ARM instruction set is missing from Cortex-M. Other CPS instructions still exists in the Cortex-M.
• SETEND doesn't exist because on-the-fly switching of data endian mode is no longer supported.
• Co-processor instructions are not supported.
• SWI instruction was renamed to SVC instruction, though the instruction binary coding is the same. However, the SVC handler code is different than SWI handler because of changes to the exception models.

Cortex-M0

Cortex-M0

Instruction set	Thumb (most), Thumb-2 (some)
Microarchitecture	ARMv6-M

The Cortex-M0 core is optimized for small silicon die size and use in the lowest price chips.

Key features of the Cortex-M0 core are:^[1]

• ARMv6-M architecture^[6]
• 3-stage pipeline.
• Instruction sets:
  • Thumb (most), missing CBZ, CBNZ, IT.
  • Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit hardware multiply with 32-bit result.
• 1 to 32 interrupts, plus NMI.

Silicon options:

• Hardware multiply speed: 1-cycle or 32-cycles.

Chips

The following microcontrollers are based on the Cortex-M0 core:

• Cypress PSoC 4
• Infineon XMC1000
• Nordic nRF51
• NXP LPC1100, LPC1200
• nuvoTon NuMicro
• Sonix SN32F700
• STMicroelectronics STM32 F0
• Toshiba TX00
• Vorago VA10800 (extreme temperature), VA10820 (radiation hardened)

The following chips have a Cortex-M0 as a secondary core:

• NXP LPC4300 (one Cortex-M4F + one Cortex-M0)
• Texas Instruments SimpleLink Wireless MCUs CC1310 and CC2650 (one programmable Cortex-M3 + one Cortex-M0 network processor + one proprietary Sensor Controller Engine)

Cortex-M0+

Cortex-M0+

Instruction set	Thumb (most), Thumb-2 (some)
Microarchitecture	ARMv6-M

The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing the use of the same compiler and debug tools. The Cortex-M0+ pipeline was reduced from 3 to 2 stages, which lowers the power usage. In addition to debug features in the existing Cortex-M0, a silicon option can be added to the Cortex-M0+ called the Micro Trace Buffer (MTB) which provides a simple instruction trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which can be added as silicon options, such as the memory protection unit (MPU) and the vector table relocation.^[2]

Key features of the Cortex-M0+ core are:^[2]

• ARMv6-M architecture^[6]
• 2-stage pipeline (one fewer than Cortex-M0).
• Instruction sets: (same as Cortex-M0)
  • Thumb (most), missing CBZ, CBNZ, IT.
  • Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit hardware multiply with 32-bit result.
• 1 to 32 interrupts, plus NMI.

Silicon options:

• Hardware multiply speed: 1-cycle or 32-cycles.
• 8 region memory protection unit (MPU) (same as Cortex-M3 and Cortex-M4).
• Vector table relocation (same as Cortex-M3 and Cortex-M4).
• Single-cycle I/O port (unique to Cortex-M0+).
• Micro Trace Buffer (MTB) (unique to Cortex-M0+).

Chips

The following microcontrollers are based on the Cortex-M0+ core:

• Atmel SAMD, SAMR, SAML, SAMC
• Cypress PSoC 4S and FM0+
• Freescale/NXP Kinetis E, EA, L, M, V1, W0
• Holtek HT32F52xxx
• NXP LPC800, LPC11E6x, LPC11U6x
• Renesas Synergy S1
• Silicon Labs/Energy Micro EFM32 Zero, Happy
• STMicroelectronics STM32 L0

Smallest ARM microcontrollers are of the Cortex-M0+ type (as of 2014, smallest at 1.6 mm by 2 mm is Kinetis KL03)^[12]

Cortex-M1

Cortex-M1

Instruction set	Thumb (most), Thumb-2 (some)
Microarchitecture	ARMv6-M

The Cortex-M1 is an optimized core especially designed to be loaded into FPGA chips.

Key features of the Cortex-M1 core are:^[3]

• ARMv6-M architecture^[6]
• 3-stage pipeline.
• Instruction sets:
  • Thumb (most), missing CBZ, CBNZ, IT.
  • Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit hardware multiply with 32-bit result.
• 1 to 32 interrupts, plus NMI.

Silicon options:

• Hardware multiply speed: 3-cycle or 33-cycles.
• Optional Tightly-Coupled Memory (TCM): 0 to 1 MB instruction-TCM, 0 to 1 MB data-TCM, each with optional ECC.
• External interrupts: 0, 1, 8, 16, 32.
• Debug: none, reduced, full.
• Data endianness: little-endian or BE-8 big-endian.
• OS extension: present or absent.

Chips

The following FPGA vendors support the Cortex-M1 as soft-cores:

• Actel/Microsemi FPGAs
• Altera FPGAs
• Xilinx FPGAs

Cortex-M3

Cortex-M3

Instruction set	Thumb, Thumb-2, Saturated Math
Microarchitecture	ARMv7-M

Key features of the Cortex-M3 core are:^[4][13]

• ARMv7-M architecture^[7]
• 3-stage pipeline with branch speculation.
• Instruction sets:
  • Thumb (entire).
  • Thumb-2 (entire).
  • 32-bit hardware multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.
  • 32-bit hardware divide (2-12 cycles).
  • saturation arithmetic support.
• 1 to 240 interrupts, plus NMI.
• 12 cycle interrupt latency.
• Integrated sleep modes.

Silicon options:

• Optional Memory Protection Unit (MPU): 0 or 8 regions.

Chips

The following microcontrollers are based on the Cortex-M3 core:

• Actel SmartFusion, SmartFusion 2
• Analog Devices ADuCM3xx
• Atmel SAM3A, SAM3N, SAM3S, SAM3U, SAM3X
• Cypress PSoC 5LP, FM3
• Holtek HT32F
• Luminary Micro/TI LM3S1968
• NXP LPC1300, LPC1700, LPC1800
• ON Semiconductor Q32M210
• Silicon Labs Precision32
• Silicon Labs/Energy Micro EFM32 Tiny, Gecko, Leopard, Giant
• STMicroelectronics STM32 F1, F2, L1, W
• Texas Instruments SimpleLink Wireless MCUs (CC1310 Sub-GHz and CC2650 BLE+ZigBee+6LoWPAN)
• Toshiba TX03

The following chips have a Cortex-M3 as a secondary core:

• Apple A9 (Cortex-M3 as integrated M9 motion Co-Processor)
• CSR Quatro 5300 (Cortex-M3 as co-processor)
• Samsung Exynos 7420 (Cortex-M3 as a DVS microcontroller)^[14]
• Texas Instruments F28, LM3, TMS470, OMAP 4470 (one Cortex-A9 + two Cortex-M3)
• XMOS XS1-XA (seven xCORE + one Cortex-M3)

Cortex-M4

Cortex-M4(F)

Instruction set	Thumb, Thumb-2, Saturated Math, DSP, FPU (SP) (M4F)
Microarchitecture	ARMv7E-M

Conceptually the Cortex-M4 is a Cortex-M3 plus DSP Instructions, and optional floating-point unit (FPU). If a core contains an FPU, it is known as a Cortex-M4F, otherwise it is a Cortex-M4.

Key features of the Cortex-M4 core are:^[5]

• ARMv7E-M architecture^[7]
• 3-stage pipeline with branch speculation.
• Instruction sets:
  • Thumb (entire).
  • Thumb-2 (entire).
  • 32-bit hardware multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.
  • 32-bit hardware divide (2-12 cycles).
  • Saturation arithmetic support.
  • DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.
• 1 to 240 interrupts, plus NMI.
• 12 cycle interrupt latency.
• Integrated sleep modes.

Silicon options:

• Optional Floating-Point Unit (FPU): single-precision only IEEE-754 compliant. It is called the FPv4-SP extension.
• Optional Memory Protection Unit (MPU): 0 or 8 regions.

Chips

The following microcontrollers are based on the Cortex-M4 core:

• Atmel SAM4L, SAM4N, SAM4S, SAM4N
• Freescale/NXP Kinetis K, W2

The following microcontrollers are based on the Cortex-M4F (M4 + FPU) core:

• Atmel SAM4C (dual core), SAM4E, SAMG
• Cypress FM4
• Freescale/NXP Kinetis K, V3, V4
• Infineon XMC4000
• Microchip CEC1302
• Nordic nRF52
• NXP LPC4000, LPC4300 (one Cortex-M4F + one Cortex-M0)
• Renesas Synergy S3, S5, S7
• Silicon Labs/Energy Micro EFM32 Wonder
• STMicroelectronics STM32 F3, F4, L4
• Texas Instruments LM4F, TM4C, MSP432
• Texas Instruments SimpleLink Wi-Fi CC3200 and CC3200MOD (FCC, IC, CE pre-certified module)
• Toshiba TX04

The following chips have either a Cortex-M4 or M4F as a secondary core:

• Freescale/NXP Vybrid VF6 (one Cortex-A5 + one Cortex-M4F)
• Freescale/NXP i.MX 6 SoloX (one Cortex-A9 + one Cortex-M4F)
• Freescale/NXP i.MX 7 Solo/Dual (one or two Cortex-A7 + one Cortex-M4F)
• Texas Instruments OMAP 5 (two Cortex-A15s + two Cortex-M4)
• Texas Instruments Sitara AM57xx (one or two Cortex-A15s + two Cortex-M4s as image processing units + two Cortex-M4s as general purpose units)

Cortex-M7

Cortex-M7(F)

Instruction set	Thumb, Thumb-2, Saturated Math, DSP, FPU (SP & DP) (M7F)
Microarchitecture	ARMv7E-M

The Cortex-M7 is a high-performance core with almost double the power efficiency of the older Cortex-M4. It features a 6-stage superscalar pipeline with branch prediction and an optional floating-point unit capable of single-precision and optionally double-precision operations.^[15][16] The instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses. If a core contains an FPU, it is known as a Cortex-M7F, otherwise it is a Cortex-M7.

Key features of the Cortex-M7 core are:

• ARMv7E-M architecture.
• 6-stage pipeline with branch speculation.
• Instruction sets:
  • Thumb (entire).
  • Thumb-2 (entire).
  • 32-bit hardware multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.
  • 32-bit hardware divide (2-12 cycles).
  • Saturation arithmetic support.
  • DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.
• 1 to 240 interrupts, plus NMI.
• 12 cycle interrupt latency.
• Integrated sleep modes.

Silicon options:

• Optional Floating-Point Unit (FPU): (single precision) or (single and double-precision), both IEEE-754-2008 compliant. It is called the FPv5 extension.
• Optional CPU cache: 0 to 64 KB instruction-cache, 0 to 64 KB data-cache, each with optional ECC.
• Optional Tightly-Coupled Memory (TCM): 0 to 16 MB instruction-TCM, 0 to 16 MB data-TCM, each with optional ECC.
• Optional Memory Protection Unit (MPU): 8 or 16 regions.
• Optional Embedded Trace Macrocell (ETM): instruction-only, or instruction and data.
• Optional Retention Mode (with ARM Power Management Kit) for Sleep Modes.

Chips

The following microcontrollers are based on the Cortex-M7 core:

• Atmel SAME70, SAMS70, SAMV70
• Freescale/NXP Kinetis KV5x^[17]
• STMicroelectronics STM32 F7,^[18] STM32 H7

Development tools

Documentation

The amount of documentation for all ARM chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since it consists of documents from the IC manufacturer and documents from CPU core vendor (ARM Holdings).

A typical top-down documentation tree is: manufacturer website, manufacturer marketing slides, manufacturer datasheet for the exact physical chip, manufacturer detailed reference manual that describes common peripherals and aspects of a physical chip family, ARM core generic user guide, ARM core technical reference manual, ARM architecture reference manual that describes the instruction set(s).

Documentation tree (top to bottom)

1. IC manufacturer website
2. IC manufacturer marketing slides
3. IC manufacturer datasheet
4. IC manufacturer reference manual
5. ARM core website
6. ARM core generic user guide
7. ARM core technical reference manual
8. ARM architecture reference manual

IC manufacturers have additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See External Links section for links to official ARM documents.

See also

• ARM architecture
• List of ARM microarchitectures
• JTAG, SWD

References

Further reading

• Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C; 2nd Edition; Yifeng Zhu, 660 pages; 2015; ISBN 978-0982692639.
• The Definitive Guide to the ARM Cortex-M0 and Cortex-M0+ Processors; 2nd Edition; Joseph Yiu; 784 pages; 2015; ISBN 978-0128032770.
• The Definitive Guide to the ARM Cortex-M3 and Cortex-M4 Processors; 3rd Edition; Joseph Yiu; 600 pages; 2013; ISBN 978-0124080829.
• Embedded Systems with ARM Cortex-M3 Microcontrollers in Assembly Language and C; 1st Edition; Yifeng Zhu; 542 pages; 2014; ISBN 978-0982692622.
• Digital Signal Processing and Applications Using the ARM Cortex-M4; 1st Edition; Donald Reay; 250 pages; 2014; ISBN 978-1118859049.
• Embedded Systems: Introduction to Arm Cortex-M Microcontrollers; 5th Edition; Jonathan Valvano; 506 pages; 2012; ISBN 978-1477508992.
• Assembly Language Programming: ARM Cortex-M3; 1st Edition; Vincent Mahout; 256 pages; 2012; ISBN 978-1848213296.
• An Introduction To Reverse Engineering for Beginners" including ARM assembly; Dennis Yurichev; online book.
• ARM Architecture Fundamentals; YouTube.

External links

Wikimedia Commons has media related to ARM Cortex-M.

ARM Cortex-M official documents

• ARM Cortex-M official website
• ARM Cortex-M Software Interface Standard (CMSIS)

ARM Core	ARM Website	ARM Generic User Guide	ARM Technical Reference Manual	ARM Architecture Reference Manual
Cortex-M0	Link	Link	Link	ARMv6-M
Cortex-M0+	Link	Link	Link	ARMv6-M
Cortex-M1	Link	Link	Link	ARMv6-M
Cortex-M3	Link	Link	Link	ARMv7-M
Cortex-M4	Link	Link	Link	ARMv7E-M
Cortex-M7	Link	Link	Link	ARMv7E-M

Quick Reference Cards

• Instructions: Thumb (1), ARM and Thumb-2 (2), Vector Floating-Point (3), arm.com
• Opcodes: Thumb (1, 2), ARM (3, 4), GNU Assembler Directives (5).

Migrating

• Migrating from 8051 to Cortex-M, arm.com
• Migrating from PIC to Cortex-M3, arm.com
• Migrating from ARM7TDMI to Cortex-M3, arm.com

Other

• Bit Banding on the STM32 microcontrollers